This analog front end is designed for High Definition Wireless or similar applications. The core incorporates dual 6-Bit ADCs, dual 6-Bit DACs along with a 1:8 data deserializer and an 8:1 data serializer. The dual ADCs and DACs can support sample rates up to 2.5 Gs/s. Both the ADCs and DACs are internally synchronized for optimum performance for use in I and Q modulation communication systems. The core also contains a low jitter 54MHz third overtone crystal oscillator and an LC VCO 2.5GHz PLL. The macro features several power down modes for system flexibility.