MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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HBM3E Controller
Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 JEDEC standards
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HBM 3 IP
- HBM3E/3 Memory Controller
- DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
- High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
- High Bandwidth Memory (HBM3E) 3 PHY for TSMC N3P
- High Bandwidth Memory (HBM3E) 3 PHY for TSMC N5P