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HBM2E PHY&Controller
Innosilicon HBM2E PHY IP is a silicon proven product with max speed up to 3600Mbps per DQ data, HBM2E memory has 1024bit DQ, total bandwidth can be 3.6Tbps. Innosilicon HBM2E PHY IP can support both 4 Hi and 8 Hi memory type.
This document describes a general layout scheme and DDR controller connecting to Innosilicon combo PHY using a DFI digital interface. All interface timing is in 1X SDR clock domain. This Interface is flexible and can be converted to any customer desired format and timing sequence. The controller to PHY interface is running at single data rate (SDR) therefore read/write bus is double width. DDR muxing is done in the PHY block together with all related per-byte lane timing adjustment.
This document describes a general layout scheme and DDR controller connecting to Innosilicon combo PHY using a DFI digital interface. All interface timing is in 1X SDR clock domain. This Interface is flexible and can be converted to any customer desired format and timing sequence. The controller to PHY interface is running at single data rate (SDR) therefore read/write bus is double width. DDR muxing is done in the PHY block together with all related per-byte lane timing adjustment.
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