HBM2/2e PHY SMIC 12/14SFE from INNOSILICON

The second-generation HBM (HBM2/2E) technology, which is outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n prefetch architecture, internal organization, 1024-bit input/output, 1.2 V I/O and core voltages as well as all the crucial parts of the original tech. Just like the predecessor, HBM2/2E supports two, four or eight DRAM devices on a base logic die (2Hi, 4Hi, 8Hi stacks) per KGSD. HBM Gen 2/2E expands capacity of DRAM devices within a stack to 8 Gb and increases supported data-rates up to 1.6 Gb/s or even to 3.2 Gb/s per pin. In addition, the new technology brings an important improvement to maximize actual bandwidth.

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