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Hardware RTP Stack for H.264 Stream Decapsulation
Implements a Real Time Transport Protocol (RTP) hardware stack that extracts H.264/NAL streams encapsulated in RTP packets.
The RTP2Η264 core is compatible with RTP packets produced by CAST’s H.264 to RTP encapsulation core (H2642RTP). The output of the RTP2Η264 can be directly connected to the input of an H.264 decoder core. Along with CAST’s UDP/IP hardware stack, the RTP2Η264 core is ideal for offloading the demanding task of RTP/UDP/IP de-capsulation from a host processor, and enables H.264 video streaming even in processor-less SoC designs.
The core is easy to integrate in systems with or without a host processor. H.264 stream and RTP packet data are input/output via dedicated streaming-capable interfaces, enabling direct connection to hardware video encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by an AXI4-Lite interface.
The RTP2Η264 core is available in RTL source or as a targeted FPGA netlist. Platforms integrating the core along with H.264 decoder, UDP/IP, and eMAC cores, are also available from CAST, and can enable rapid development of video over IP systems.
The RTP2Η264 core is compatible with RTP packets produced by CAST’s H.264 to RTP encapsulation core (H2642RTP). The output of the RTP2Η264 can be directly connected to the input of an H.264 decoder core. Along with CAST’s UDP/IP hardware stack, the RTP2Η264 core is ideal for offloading the demanding task of RTP/UDP/IP de-capsulation from a host processor, and enables H.264 video streaming even in processor-less SoC designs.
The core is easy to integrate in systems with or without a host processor. H.264 stream and RTP packet data are input/output via dedicated streaming-capable interfaces, enabling direct connection to hardware video encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by an AXI4-Lite interface.
The RTP2Η264 core is available in RTL source or as a targeted FPGA netlist. Platforms integrating the core along with H.264 decoder, UDP/IP, and eMAC cores, are also available from CAST, and can enable rapid development of video over IP systems.
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Block Diagram of the Hardware RTP Stack for H.264 Stream Decapsulation
H.264 IP
- Enhanced Multi-Format Encoder Supporting AV1
- Up To 5 MPixel Multi-Format Encoder
- 4K/ 8K LCEVC Video Decoder
- H.264 High Profiles Encoder - High 10, High 4:2:2 and High 4:4:4 (12 bit 4:2:2 or 4:2:0) Profiles
- H.264 Baseline Encoder with compressed reference frame store
- AV1/HEVC/AVC Single-core Encoder Video IP