You are here:
Hardware 3DES Accelerator
• Designed for low latency and high throughput applications in embedded systems
• Specially optimized for hardware acceleration of Linux CryptoAPI subsystem
• DES/3DES encryption and decryption
• ECB & CBC modes
• All possible 3DES options are supported (EEE, EED, EDE, EDD, DEE, DED, DDE, DDD)
• Complete implementation of FIPS 46-3
• ATSC descrambling is supported for DTV applications(support for short-blocks in 3DES-CBC mode)
• 32-bit AMBA APB Interface
• 64-bit AMBA AXI Master
• 4 bus cycles for DES
• 12 bus cycles for 3DES
• Asynchronous bulk operations in DMA mode for high performance on large data sets
• Synchronous single-word operations for low-latency encryption operations, can be executed during bulk asynchronous transaction
• Specially optimized for hardware acceleration of Linux CryptoAPI subsystem
• DES/3DES encryption and decryption
• ECB & CBC modes
• All possible 3DES options are supported (EEE, EED, EDE, EDD, DEE, DED, DDE, DDD)
• Complete implementation of FIPS 46-3
• ATSC descrambling is supported for DTV applications(support for short-blocks in 3DES-CBC mode)
• 32-bit AMBA APB Interface
• 64-bit AMBA AXI Master
• 4 bus cycles for DES
• 12 bus cycles for 3DES
• Asynchronous bulk operations in DMA mode for high performance on large data sets
• Synchronous single-word operations for low-latency encryption operations, can be executed during bulk asynchronous transaction
查看 Hardware 3DES Accelerator 详细介绍：
- 查看 Hardware 3DES Accelerator 完整数据手册
- 联系 Hardware 3DES Accelerator 供应商
DES IP
- Secure-IC's Securyzr™ Tunable DES - Triple DES (ECB, CBC, CTR) accelerator - optional SCA protection
- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes
- DES and Triple DES (TDES or 3DES) encryption and decryption coprocessor
- Ultra-Compact Data Encryption Standard (DES/3DES) Core
- Triple DES core
- DES/TDES core