AV1/HEVC/AVC/VP9 Dual-core Video Codec HW IP: 8K60fps/4K240fps in Real-time
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Hamming Code ECC
The RTL is configurable for number of message bits that need ECC protection. Once RTL is generated it is fixed.
1- RTL has no RAMS/ROMS/Flip Flops.
2- No iterative Feedback in the pipeline
It can do 1 bit error correction and 2 bit error detection.
It is a completely asynchronous design for encoder and decoder
1- RTL has no RAMS/ROMS/Flip Flops.
2- No iterative Feedback in the pipeline
It can do 1 bit error correction and 2 bit error detection.
It is a completely asynchronous design for encoder and decoder
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Block Diagram of the Hamming Code ECC
