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H.264 HD DECODER - Supports 1080p60. 4:2:2. 10 Bits
VYUsync’s H.264 1080p60, 4:2:2, 10-bit Decoder Core is a highly optimized, high resolution decompression engine targeted primarily at FPGAs. The leading broadcast companies have incorporated VYUsync’s H.264 Decoder IP in their end products and more than 100,000 products have been shipped. It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The Decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of the end users.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The Decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of the end users.
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