Scalable UHD H.264 Encoder - Ultra-High Throughput, Full Motion Estimation engine
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H.264 CODEC for Xilinx FPGAs
The H.264 CODEC is capable of being synthesized in Xilinx FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 3 clocks/pixel. Typical clock rate in an Xilinx SPARTAN 6 is 70Mhz. Typical clock rate in a Xilinx Virtex 6 is 140MHz. Multiple cores can be used for processing larger size or higher bandwidth images. Uses FPGA specific DDR 3 controller and microprocessor soft core. Built in Decoder that can decode A2e H.264 encoded streams.
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h.264 IP
- Enhanced Multi-Format Encoder Supporting AV1
- Up To 5 MPixel Multi-Format Encoder
- 1080p60 Multi-Format Decoder IP
- 4K/8K Scalable Multi-Format Video Decoding IP Core
- Scalable UHD H.264 Encoder - Ultra-High Throughput, Full Motion Estimation engine
- H.264 Baseline Encoder with compressed reference frame store