H.264 CODEC for Xilinx FPGAs

The H.264 CODEC is capable of being synthesized in Xilinx FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 3 clocks/pixel. Typical clock rate in an Xilinx SPARTAN 6 is 70Mhz. Typical clock rate in a Xilinx Virtex 6 is 140MHz. Multiple cores can be used for processing larger size or higher bandwidth images. Uses FPGA specific DDR 3 controller and microprocessor soft core. Built in Decoder that can decode A2e H.264 encoded streams.

• 查看 H.264 CODEC FPGA Core 完整数据手册
• 联系 H.264 CODEC FPGA Core 供应商