USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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GSMC 0.18um Voltage Detector
This IP is a Voltage Detector (VDT) circuit for power management application. When the supply voltage (AVDD33) increases above the detection level (VTHR), the output VOK33 will assert a logical high (VOH). When AVDD33 decreases below the detection level (VTHF), the output VOK33 will assert a logical low (VOL). This IP cannot operate stand-alone. It needs a 1.2V reference and 1.75uA bias current from another VeriSilicon IP, GSMC18_PRG_03.
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