The present IP is a VCC Detector (VDT) circuit. It detects the voltage level of both core (AVDD18) and I/O (AVDD33). It will generate four flag signals，VDT18H, VDT18L, VDT33H and VDT33L, when AVDD18 and AVDD33 reach the trigger point. This IP contains four comparators and a reference voltage from external bandgap. The output may be in the wrong voltage level during the power-up phase before the bandgap becomes stable.
- Process: GSMC 0.18um 1.8v/3.3v 1P6M IBG Logic process, or GSMC 0.18um 1.8v/3.3v 4P6M IBG eflash process
- Supply voltage: 1.8v+/- 10%, 2.0~3.6v
- Average current: 20uA
- Operating junction temperature: -40°C ~ +25°C ~ +125°C