32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
GSMC 0.15umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
The compiler supports a comprehensive range of word and bits lengths. While satisfying speed and power requirements, it is optimized for area efficiency.
VeriSilicon GSMC LP Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, 6 or 7 as the top metal. Dummy bit cells are embedded with the intention to enhance reliability.
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