DVB-S2X LDPC BCH Decoder and Encoder IP Core
MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
LPDDR5X/5/4X/4 PHY for 16nm
ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
创飞芯0.13μm eFuse OTP IP 应用于CMOS 图像传感器量产 突破1.5 万片
芯原推出业界领先的车规级智慧驾驶SoC设计平台
芯驰科技扩大Arteris NoC IP技术授权
How to design secure SoCs, Part II: Key Management
MIPI in FPGAs for mobile-influenced devices
Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
Silicon Creations Presents Architectures and IP for SoC Clocking
Ethernet Evolution: Trends, Challenges, and the Future of Interoperability
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