Tensilica AI Boost
Sensor fusion solutions for augmented and virtual reality, robotics, motion controllers, and IoT
1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
NVM EEPROM NeoEE in Grace (180nm, 160nm, 130nm, 110nm)
创飞芯0.13μm eFuse OTP IP 应用于CMOS 图像传感器量产 突破1.5 万片
芯原推出业界领先的车规级智慧驾驶SoC设计平台
芯驰科技扩大Arteris NoC IP技术授权
How to design secure SoCs, Part II: Key Management
MIPI in FPGAs for mobile-influenced devices
Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
Silicon Creations Presents Architectures and IP for SoC Clocking
Ethernet Evolution: Trends, Challenges, and the Future of Interoperability
Connected AI is More Than the Sum of its Parts
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