This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz.By setting DM [5:0] and DN [10:0] to different values according to different FREF, CLK will be locked at the multiples of input frequency.CLKO is CLK divided by DP1[2:0]&DP2[2:0].
- Process: GF 28nm SLP 1.0V/2.5V CMOS process
- Supply voltage: 2.25V<=AVDD<=2.75V,0.9V<=DVDD(AVDD2)<=1.1
- Mos device type: nfet, pfet, zgnfet, zgpfet,vncap
- Operating current: AVDD<1.2mA(1GHz) AVDD<4.8mA(3.2GHz)
- Operating junction temperature: - 40°C ~ +25°C ~ +125°C
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