GF L12LLP 12nm Clock Generator PLL - 500MHz-2500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values.

• 查看 GF L12LLP 12nm Clock Generator PLL - 500MHz-2500MHz 完整数据手册
• 联系 GF L12LLP 12nm Clock Generator PLL - 500MHz-2500MHz 供应商