MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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Generic Polar FEC Codec
Creonic has flexible Polar decoder architecture to fulfil different customer requirements.
The IP core has been demonstrated on internal conferences and shows. An FPGA demonstrator is available for customer presentations.
Available for ASIC and FPGAs (Xilinx, Intel, Microchip).
The IP core has been demonstrated on internal conferences and shows. An FPGA demonstrator is available for customer presentations.
Available for ASIC and FPGAs (Xilinx, Intel, Microchip).
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