MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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General Video Interface HS Receiver PHY
特色
- General Video Interface HS Receiver PHY IP
- Next generation HD interface with low EMI
- Fully comply with V-By-One HS V1.3 electrical specification
- Low power consumption for multiple lane application
- Compact size: 0.1mm2 per lane including PMU and IO PAD
- Support Data rate: 0.6Gbps~4Gbps per lane
- 9bit/10bit parallel interface
- Implemented CTLE to compensate channel loss
- Integrated on-die termination resistors
- Tolerance frequency offset up ±15000ppm
- Build-in self-test facility
- AC coupling
- Support up to x16 lanes
- Support BGA, QFN/QFP package
- ESD performance: HBM >6000V / IEC >6000V
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HS Receiver IP
- MIPI DSI Receiver Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um HS/FSG process
- Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process
- Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
- V-By-One HS Receiver PHY