MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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General Purpose IO IP, UMC 0.18um G2 process
UMC 0.18um 1.8/3.3V GII Logic process Generic mini IO.
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