MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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General Purpose IO IP, 5V tolerance, UMC 55nm SP process
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate process 5V Tolerant BOAC IO Cell Library.
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