MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
GPIO Controller
- Level sensitive, single edge triggered or level change
- Active high or low respectively rising edge or falling edge
- Individual interrupt enable register and status flags
查看 General Purpose Input / Output Controller (GPIO) 详细介绍:
- 查看 General Purpose Input / Output Controller (GPIO) 完整数据手册
- 联系 General Purpose Input / Output Controller (GPIO) 供应商