You are here:
Gen2 DDR multiPHY in TSMC (28nm)
Synopsys DesignWare® Gen 2 DDR multiPHY IP cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard LPDDR2, LPDDR3, and DDR3 SDRAM memories. The Gen 2 DDR multiPHY IP supports the entire range of DDR3 SDRAM speeds, from DDR3-666 through DDR3-2133, LPDDR2 SDRAMs from 0 to 1066 Mbps and LPDDR3 SDRAMs from 0 to 2133 Mbps. The Gen 2 DDR multiPHY IP are compiled into a hard macro that is optimized for specific foundry nodes. Each Gen 2 DDR multiPHY is constructed from the following libraries of components: application-specific SSTL I/O library, a single address/command macro block, multiple byte wide data macro blocks instantiated as many times as required to accommodate the memory channel width and separate PLL macrocells that directly abut to the address/command macro block and data macro blocks.
A key component of the DesignWare Gen 2 DDR multiPHY is the extensive in-system data training/calibration capability that is used to maximize the overall timing budget and improve system reliability. The DesignWare Gen 2 DDR multiPHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling. The Gen 2 DDR multiPHY also supports per-bit deskew calibration of the address/command bus for LPDDR3 SDRAMs.
A key component of the DesignWare Gen 2 DDR multiPHY is the extensive in-system data training/calibration capability that is used to maximize the overall timing budget and improve system reliability. The DesignWare Gen 2 DDR multiPHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling. The Gen 2 DDR multiPHY also supports per-bit deskew calibration of the address/command bus for LPDDR3 SDRAMs.
查看 Gen2 DDR multiPHY in TSMC (28nm) 详细介绍：
- 查看 Gen2 DDR multiPHY in TSMC (28nm) 完整数据手册
- 联系 Gen2 DDR multiPHY in TSMC (28nm) 供应商
Video Demo of the Gen2 DDR multiPHY in TSMC (28nm)
SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. Meet your specific design targets by using Synopsys’ high-performance, silicon-proven DDR memory interface IP solutions compliant with the latest JEDEC standards.