The IntelliProp IPC-GZ201A-ZM Gen-Z Switch is an IP Core that allows companies to build Gen-Z compliant components. The IPC-GZ201A-ZM is compliant with the Gen-Z 1.1 Core Specification and provides support for all OpCodes and OpClasses falling under the Explicit OpClass packet format. The IPC-GZ201A-ZM IP core is designed for integration into FPGA and ASIC developments to minimize development time and familiarization required to develop this IP independently. The IPC-GZ201A-ZM is fully verified in pseudo random simulation.
The IPC-GZ201A-ZM Gen-Z Thin Switch Layer IP Core provides a streaming interface to connect one or more IPC-GZ198A-ZM Gen-Z Link Layer IP Cores to one or more upper layer cores (Requester, Responder, etc). The Thin Switch houses the Gen-Z Core Structure and several other key Gen-Z structures that define a singular Gen-Z component and enable end-to-end packet routing between the upper layer protocol engine(s) and the appropriate Link Layer Core (Gen-Z Interface).
The IPC-GZ201A-ZM Gen-Z Standard Switch Layer IP Core provides all of the features of the Thin Switch Layer IP Core. In addition, the Standard Switch Layer enables end-to-end packet relay between Link Layers.
The Gen-Z Thin and Standard Switch Layer IP Cores expose several synthesis time parameters and a memory-mapped register interface for static and dynamic configuration flexibility.
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.1 Core Specification
- Explicit Op-Class format support (Core64, Control, Atomic, etc.)
- AXI-Stream and AXI-MM system interconnects
- Avalon-ST and Avalon-MM system interconnects
- Multi-Link Layer (Gen-Z Interface) support
- Multi-Requester Layer support
- Multi-Responder Layer support
- Gen-Z Core Structure support
- Gen-Z OpCode Set Structure support
- Gen-Z Component Destination Table, SSDT, RIT, REQ-VCAT, and RSP-VCAT support
- Gen-Z Component Switch Structure support
- Single Subnet/Single Route destination packet routing support
- Single Subnet/Single Route packet relay support
- Multi-Action VC remapping support
- Documentation: Comprehensive User Documentation
- Design File Formats: Encrypted Verilog/SystemVerilog
- Constraints Files: Provided per FPGA
- Verification: ModelSim verification model
- Instantiation Templates: Verilog
- Reference Designs & Application Notes: Synthesis and place and route scripts
- Simulation Tool Used: ModelSim (contact IntelliProp for latest versions supported)
- Support: The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date.
- Applications that require an industry compliant Gen-Z component
- Applications that require a Gen-Z component that supports packet relay
- Requester/Responder/Switch component attaching to a Gen-Z Fabric