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Gen-Z Responder IP Core
The IntelliProp IPC-GZ189A-DT Gen-Z Responder is an IP Core that allows the building of Gen-Z compliant media devices. The IPC-GZ189A-DT is compliant with the Gen-Z 1.1 Core Specification and provides support for all OpCodes and OpClasses falling under the Explicit OpClass packet format. The IPC-GZ189-DT IP core is designed for integration into FPGA and ASIC developments to minimize development time and familiarization required to develop this IP independently. The IPC-GZ189A-DT is fully verified in pseudo random simulation.
The IPC-GZ189A-DT Gen-Z Responder IP Core provides a system attached fabric interface for sending and receiving end-to-end Gen-Z packets. The Responder IP Core can be directly attached to the Link Layer IP Core or attached to an internal switch that connects multiple Requester, Responder, or Link Layer IP Cores.
The Responder can be dynamically configured to route different packet OpCode and OpClass combinations over multiple streaming or memory-mapped interfaces allowing flexibility in handling methods for requests and responses. Packet consumption or generation through the system interfaces can be handled by either user logic state machines or by an embedded processor.
The IPC-GZ189A-DT Gen-Z Responder IP Core provides a system attached fabric interface for sending and receiving end-to-end Gen-Z packets. The Responder IP Core can be directly attached to the Link Layer IP Core or attached to an internal switch that connects multiple Requester, Responder, or Link Layer IP Cores.
The Responder can be dynamically configured to route different packet OpCode and OpClass combinations over multiple streaming or memory-mapped interfaces allowing flexibility in handling methods for requests and responses. Packet consumption or generation through the system interfaces can be handled by either user logic state machines or by an embedded processor.
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