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Gen-Z Physical Layer for PCIe IP Core
The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe Phy. The IPC-GZ197A-ZM is compliant with the Gen-Z 1.1 Physical Layer Specification and provides support for multi-lane links, lane reversal, and link width reduction. The IPC-GZ197A-ZM IP Core is designed for integration into FPGA and ASIC developments to minimize development time and familiarization required to develop this IP independently. The IPC-GZ197A-ZM is fully verified in pseudo random simulation.
The IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe provides a Gen-Z 1.1 Physical Layer Specification compliant Physical Layer Abstraction interface for Gen-Z communication over a PCIe Phy. The IP core is scalable to support up to 16 lanes in a single link and most PLA data widths. The IntelliProp Bus Interface connection to the Transceiver Wrapper allows for register configurable transmitter and receiver equalization settings of the transceivers. The IP core manages initialization and configuration of the transceivers as well as striping and scrambling/descrambling of link layer data over the PLA interface.
The IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe provides a Gen-Z 1.1 Physical Layer Specification compliant Physical Layer Abstraction interface for Gen-Z communication over a PCIe Phy. The IP core is scalable to support up to 16 lanes in a single link and most PLA data widths. The IntelliProp Bus Interface connection to the Transceiver Wrapper allows for register configurable transmitter and receiver equalization settings of the transceivers. The IP core manages initialization and configuration of the transceivers as well as striping and scrambling/descrambling of link layer data over the PLA interface.
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