Fractional N Clock PLL

The programmable Fractional-N PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplication factor.This is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using convenient reference frequencies.The PLL except modulator is implemented based on differential CML logic for robust operation under strong noise coupling through power, ground and substrate. The generated clock can be locked to the input source yet adjusted to a fine-degree of precision, and may be adjusted on-the-fly to maintain a relatively drifting local clock need. The updatable programmable fractional feedback divider is provided for this purpose. Differential circuit techniques are employed to attain low jitter in the noisy environment typical of multi-million gates digital chip.

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