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FPGA Dual HDLC Serial Port
The Dual HDLC controller provides two full-duplex HDLC channels, each with 512-byte data FIFO buffers for both directions. Recognizing that in most applications the various HDLC options rarely change, the design uses pins to control these options rather than dedicated control registers. This essentially eliminates initialization requirements.
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FPGA Dual HDLC Serial Port IP
- SPI Master / Slave Controller w/FIFO (APB Bus)
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
- SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
- SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
- SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)