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FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
The FPD LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSYNC, Data Enable, and Pixel Clock to a FPD LVDS compliant display panel via 3 or 4 LVDS Differential Data Pairs and 1 LVDS Differential Clock Pair.
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Block Diagram of the FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
FPD LVDS Display Interface IP
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane
- LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)
- FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)
- Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew