FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability
National Semiconductor openLDI specification v0.95
dated May 13th 1999 that allow the transfer of digital
display data between a display source and a display
device.
This receiver converts 5 LVDS, (low voltage differential
signaling) data streams, into 30bits (single pixel) CMOS
data plus 5 control signals (VSYNC, HSYNC, DE, and 2
user-defined signals).
Thanks to its innovative lane to lane de-skew mechanism this macro can operate up to a maximum pixel rate of 170Mhz, LVDS data line speed is 1.19Gb/s, providing a total maximum bandwidth of 5.95Gb/s (744Mbytes per second).
2 Instances can provide FullHD @ 120Hz data rate !
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FPD IP
- LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
- LVDS/FPD Link IP, Silicon Proven in GF 28LPe
- FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane
- LVDS serdes 28:4 channel compression TX 20-170Mhz