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Four Channel LVDS Serializer
The 28FDSOI-LVDS-4CH-TX-1250-PLL is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data is 7/10 bits wide per channel. The input clock is 25MHz to 165MHz. The serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
特色
- 25-165 MHz clock support
- Up to 1250 Mbps bandwidth/channel
- Up to 5.0 Gbps data throughput
- Low power CMOS design
- LVDS for low EMI
- PLL requires no external components
- Core Voltage & 1.8V dual power supply
- Optional transmit pre-emphasis
- 7/10 bit serial data transmitted per pixel clock per channel
- Rising/falling edge data strobe
- Compatible with TIA/EIA-644 LVDS Standard
优势
- One IP supports both D-PHY and LVDS standards
可交付内容
- Data Sheet
- GDSII
- LVS Netlist
- Integration Guidelines
- Synopsys timing Model
- Behavioral Model
- LEF File for P&R
应用
- Mobile
- IoT
- Display
- Camera
- Virtual Reality
- Augmented Reality
Block Diagram of the Four Channel LVDS Serializer
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Serializer IP
- 1.25 Gbps 4-Channel LVDS Serializer with Pre-emphasis
- Sub-LVDS receiver followed by 1:4 de-serializer
- 32:1 serializer followed by sub-LVDS drivers
- Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
- Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- MPEG TS Serializer