- Configurable link widths provides bandwidth where needed and allows a reduction in the number of wires required to interconnect IP cores.
- Fewer wires allow tighter placement of IP blocks and a smaller chip floorplan.
- NoC bandwidth regulation reduces average transaction latency in the full chip while providing the lowest latency to the most critical cores.
- Interconnect configuration and seamless IP reuse and integration is enabled by the FlexArtist development tools.
- FlexVerifier, a powerful automated testbench generator.
- FlexVerifier creates and runs a comprehensive set of system and IP tests on the configured interconnect to achieve 100 percent coverage, along with functional coverage tests on all the system interfaces to ensure complete interoperability.
- Real-time on-the-fly traffic prioritization for bandwidth regulation
- Efficient SDRAM memory access scheduling
- Fully configurable internal network topology of link widths, arbiters, FIFOs, pipeline stages, rate adapters, traffic urgency, bandwidth regulators, and memory schedulers
- TLM 2.0 compliant SystemC simulation model generation
- Higher margins
- Fewer wires
- Smaller die size
- Reduce power consumption
- Shorter schedules
- Meet timing requirements the first time
- Automate interconnect setup and verification
- FlexNoC interconnect IP
- FlexArtist configuration tool
- FlexVerifier automated testbench generator
- Documentation, training, and support.
- Automotive, Mobility, Wireless, Consumer Electronics, IoT, Server, Networking and Industrial SoCs
Video Demo of the FlexNoC互连IP
Understanding how on-chip interconnect and DDR memory controller configurations impact the system performance, power and cost of multicore SoCs requires deep visibility. Sponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with the deep, system-level analysis they need to configure and optimize Quality-of-Service (QoS) features earlier in the design cycle.