Fibre Channel Link Layer Core
At the physical layer, the core is built for connecting to ASIC/FPGA embedded SERDES or discrete SERDES parts. The user interface of the core provides an intuitive streaming interface for application designers. The user interface within the core also includes cross clocking logic making integration into the larger design extremely simple.
This core has been used on a diverse set of applications, from enterprise storage to aerospace electronics, and on a wide range of parts at varying operating operating rates. The core comes with test-benches and example code, making design integration a straightforward task.
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Block Diagram of the Fibre Channel Link Layer Core
Fibre Channel Core IP
- Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
- Fibre-Channel Transceiver
- 1.06/2.125/4.25 Gbps Fibre Channel and Backplane SerDes
- Fibre Channel ASM (Anonymous Subscriber Messaging) Core
- 32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
- Fibre Channel ULP (Upper Layer Protocol) Core