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FFT/IFFT
The fast Fourier transform (FFT) MegaCore® function is a high-performance, highly parameterizable FFT processor. The FFT function implements a radix-2/4 decimation-in-frequency (DIF) FFT algorithm for transform lengths of 2m where 6 ? m ? 14, internally using a block-floating-point architecture to maximize signal dynamic range in the transform calculation.
The FFT MegaCore function accepts, as input, a complex data vector of length N (in two?s complement format) and outputs the transform-domain complex vector in natural order. An accumulated block exponent is output to indicate any data scaling that has occurred during the transform to maintain precision and maximize the internal signal-to-noise ratio. Transform direction is specifiable on a per-block basis via an input port.
The FFT MegaCore function has the following options:
* Radix-4 and mixed radix-2/4 implementations
* Variable transform length
* Block floating-point architecture?maximizes internal signal dynamic range
* Use of internal memory
The FFT MegaCore also:
* Is optimized to use digital signal processing (DSP) blocks and TriMatrix memory architecture
* Uses embedded multipliers
* Has intellectual property (IP) functional simulation models for use in Altera supported VHDL and Verilog HDL simulators
The FFT MegaCore function accepts, as input, a complex data vector of length N (in two?s complement format) and outputs the transform-domain complex vector in natural order. An accumulated block exponent is output to indicate any data scaling that has occurred during the transform to maintain precision and maximize the internal signal-to-noise ratio. Transform direction is specifiable on a per-block basis via an input port.
The FFT MegaCore function has the following options:
* Radix-4 and mixed radix-2/4 implementations
* Variable transform length
* Block floating-point architecture?maximizes internal signal dynamic range
* Use of internal memory
The FFT MegaCore also:
* Is optimized to use digital signal processing (DSP) blocks and TriMatrix memory architecture
* Uses embedded multipliers
* Has intellectual property (IP) functional simulation models for use in Altera supported VHDL and Verilog HDL simulators
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