Facilitates configuration of peripheral blocks

CoreConfigP facilitates the configuration of peripheral blocks in a SmartFusion®2 or IGLOO®2 device. The blocks of interest are the double data rate (DDR) memory controllers and the high speed serial interface blocks (SERDESIF). CoreConfigP has a mirrored master advanced peripheral bus (APB) port and several mirrored slave APB ports. The mirrored master APB port should be connected to the FIC_2_APB_MASTER master port of the microcontroller subsystem (MSS) in the case of SmartFusion2, or the high performance memory subsystem (HPMS) in the case of IGLOO2. The mirrored slave APB ports should be connected to the APB slave ports of the blocks that need to be configured.

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