256x1 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
eUSB 3.1 Gen 2 Device Controller - Software Enumeration, FIFO Interface
It has been designed to provide simplicity and flexibility along with highest throughput around 8.5Gbps. Avalon/AXI interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
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Block Diagram of the eUSB 3.1 Gen 2 Device Controller - Software Enumeration, FIFO Interface

Video Demo of the eUSB 3.1 Gen 2 Device Controller - Software Enumeration, FIFO Interface
This video showcase the performance achieved for the eUSB 3.1 Gen 2 Device Controller IP Core on Arria 10 GX development kit.
USB 3.1 device Controller IP
- USB 3.1 Controller IP
- USB 3.1 SuperSpeed Device Controller (USB-IF Certified)
- USB 3.1 SuperSpeed+ (Gen2) Device Controller (USB-IF Certified)
- USB 3.1 SuperSpeed Dual-Role Device Controller (USB-IF Certified)
- USB 3.1 SuperSpeed+ (Gen2) Dual-Role Device Controller (USB-IF Certified)
- USB 3.1 Gen1 / Gen2 Device Controller IP