28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
ETR101290 IP core
• ETR101290 is CPU programmable
• It includes all the processing stages to analyze PSI/SI tables and ETR101290 errors
• Each subpart of any priority item can be analyzed or not
• An output event signal can inform a CPU of a new incoming error
• Configurable output UART can log selected detected errors
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