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Ethernet TSN Switch IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide an optimized custom IP core within days of receiving customer requirements.
Packet Architects can provide IP cores with a full range of Ethernet switching and routing features such as IPv4/IPv6 routing, L2 switching, MPLS switching, advanced VLAN handling, TSN, IPsec, MACsec, classification, automatic learning etc.
The core is built around a shared buffer memory architecture providing wire-speed switching and routing on all ports without head of line blocking. It offers dynamic allocation of packet buffers per port and priority to avoid starvation due to over-allocation. Advanced QoS features allow the most timing critical packets to get minimal delay while providing fairness between traffic classes.
No initial software setup is required and due to the hardware learning for MAC addresses the core is ready to receive and forward Ethernet frames immediately once powered up. There is a high performance processor interface for register configuration, and a high performance dedicated CPU port for slow path processing of packets.
The design is optimized for both FPGA and ASIC technology but does not have any dependencies on the underlying technology. If the target technology has TCAMs these can be utilized.
Packet Architects can provide IP cores with a full range of Ethernet switching and routing features such as IPv4/IPv6 routing, L2 switching, MPLS switching, advanced VLAN handling, TSN, IPsec, MACsec, classification, automatic learning etc.
The core is built around a shared buffer memory architecture providing wire-speed switching and routing on all ports without head of line blocking. It offers dynamic allocation of packet buffers per port and priority to avoid starvation due to over-allocation. Advanced QoS features allow the most timing critical packets to get minimal delay while providing fairness between traffic classes.
No initial software setup is required and due to the hardware learning for MAC addresses the core is ready to receive and forward Ethernet frames immediately once powered up. There is a high performance processor interface for register configuration, and a high performance dedicated CPU port for slow path processing of packets.
The design is optimized for both FPGA and ASIC technology but does not have any dependencies on the underlying technology. If the target technology has TCAMs these can be utilized.
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Block Diagram of the Ethernet TSN Switch IP Core - Efficient and Massively Customizable
ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E)
- 112G Ethernet PHY in TSMC (N7, N5, N3P)
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency