Scalable multicore architecture for a range of macrocells, small cells, cloud-RAN, DFE/DPD/ and more
Ethernet TSN MAC 40G/100G
The MAC-core performs the Link function of the 40G/100G Ethernet Standard and is a low latency cut-through implementation, while keeping size at a minimum.
The core is fully configurable, interfaces easily to standard 40G/100G PCS due to its CGMII interface, and can optionally include IEEE1588 Timestamping Unit (TSU).
The Ethernet MAC Core, on the Client side, implements a 256-bit AXI-S interface for Express and Preemptable traffic respectively while having a standard 256-bit CGMII interface on the PHY side.
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Block Diagram of the Ethernet TSN MAC 40G/100G

MAC IP
- Gigabit Ethernet 802.3 MAC - Media Access Controller
- CEVA-RivieraWaves UWB turnkey MAC and PHY platform IP
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
- 400G/200G/100G Ethernet MAC
- 800G/400G/200G Ethernet MAC
- RivieraWaves 802.11n (Wi-Fi 4) 1x1 20/40MHz MAC & modem