Comcores PCS IP core is a silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2015. The IP-core supports 1G and 2.5G line rates. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a Gigabit Media Independent Interface (GMII) or Serial Gigabit Media Independent Interface (SGMII). On one side it interfaces to a Serdes device and on the application side it has a port for GMII/SGMII Ethernet signals.
The IP-core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.