The Ethernet Media Access Controller IP is an embedded Fast Ethernet controller module. It is compliant with IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE802.3ab specification for 1000Mbps Ethernet MAC. The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. The controller provides half- or full-duplex operation, supports jumbo frames, and optionally provides a reach set of statistics counters enabling station management. The IP core is designed for SoC and mobile applications such as integrated networking devices, PCI-Express Ethernet controllers, and Ethernet adapter cards. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint. Integration with an Ethernet PHY is straightforward, as the controller core supports the Media Independent Interface (MII) and the Gigabit Media Independent Interface (GMII) physical layer interface standards.
- Compliant to IEEE 802.3-2002 specification
- Comply with IEEE 802.3u MII interface.
- Supports full duplex flow control - IEEE 802.3
- Supports VLAN - compliant to IEEE 802.3, 802.1Q
- Supports 32-bit memory local bus interface
- Jumbo and Short frame support
- Flexible address filtering
- Extensive statistics counters
- Flexible address filtering modes and inverse address filtering
- 64-bit hash table to filter multicast addresses
- Full Duplex/Half Duplex capability for 10M/100M MAC
- MII, GMII and RGMII interface support
- Automatic generation of FCS and PAD
- Supports MDIO for PHY management
- Management counters for RMON and IEEE 802.3
- Automatic detection and checking of PAUSE frames
- Option to block PAUSE frames
- Maskable interrupts for major hardware events
- Store-forward and cut-through mode support
- Line and system loopback support
- Highly Configurable: Hardware & Software options Line
- Easy-to-use industry-standard test environment and ease of integration.
- Feature-rich, highly flexible, scalable, configurable and timing friendly design
- Unencrypted source code allows easy implementation
- Verified with one VIP
- Customer training available
- optimized for high performance, link utilization, low latency, low power, and low gate count.
- Reuse Methodology Manual guidelines (RMM) compliant Verilog code ensured using Spyglass
- The core is available in Verilog RTL or as targeted FPGA netlist
- It is deliverable including an extensive testbench, comprehensive documentation, and a sample Linux driver.
- It can be used in any SoC design requiring Ethernet connectivity.
- Can be used in Embedded system like IP STB, STB, etc.
- It can be used in Networking and communications like Network Interface Adapter.