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Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s
The DESPI is a fully configurable eSPI master/slave device supporting all features described in Enhanced Serial Peripheral Interface Base Specification rev. 1.0. The DESPI master is to be used by the microcontroller to communicate with eSPI peripheral devices. The DESPI slave is to be used as an eSPI peripheral device, e.g. an Embedded Controller attached to the Intel CPU system.
The eSPI bus is an LPC bus improvement. The serial clock line (_sck) synchronizes shifting and sampling of the information on the IO lines. It is a technology-independent design that can be implemented in a variety of process technologies. The DESPI is flexible enough to interface directly with numerous peripherals. The system might be configured as well as master as slave. Depending on the core configuration, the _in or _out lines are utilized. The serial clock may be up to 66MHz. The DESPI is also capable of simple, dual, and quad SPI transfers. The DESPI is fully customizable, which means it is delivered in the exact configuration meeting users’ requirements. Additionally, the DESPI module is equipped with receiver and transmitter FIFOs able to store up to 4096+16 bytes (header and data payload or separate buffers for every eSPI channel and for posted/non-posted transfers), a customizable Peripheral Channel Memory and IO port, Virtual Wire lines and event lines.
The controller is capable to operate in several eSPI configurations: Single Master- Single Slave, Single Master – Multiple Slaves.
The eSPI bus is an LPC bus improvement. The serial clock line (_sck) synchronizes shifting and sampling of the information on the IO lines. It is a technology-independent design that can be implemented in a variety of process technologies. The DESPI is flexible enough to interface directly with numerous peripherals. The system might be configured as well as master as slave. Depending on the core configuration, the _in or _out lines are utilized. The serial clock may be up to 66MHz. The DESPI is also capable of simple, dual, and quad SPI transfers. The DESPI is fully customizable, which means it is delivered in the exact configuration meeting users’ requirements. Additionally, the DESPI module is equipped with receiver and transmitter FIFOs able to store up to 4096+16 bytes (header and data payload or separate buffers for every eSPI channel and for posted/non-posted transfers), a customizable Peripheral Channel Memory and IO port, Virtual Wire lines and event lines.
The controller is capable to operate in several eSPI configurations: Single Master- Single Slave, Single Master – Multiple Slaves.
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