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Enhanced Neural Processing Unit for functional safety providing 49,152 MACs/cycle of performance for AI applications
The ASIL B or D Ready DesignWare ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of Advanced Driver Assistance Systems (ADAS) and autonomous vehicle systems that require artificial intelligence (AI) for vision, RADAR, LiDAR and / or sensor fusion.
The NPX6FS NPUs include state-of-the-art hardware safety features including diagnostic error injection, windowed watchdog timers, error classification, and software diagnostic tests as well as safety monitors and lockstep capabilities for safety-critical modules. The processors include dedicated safety mechanisms for ISO 26262 compliance and address the mixed criticality and virtualization requirements of next-generation zonal architectures.
Comprehensive safety documentation, including safety manuals, FMEDA and DFMEA reports, accelerate SoC-level functional safety assessments. These features enable designers to achieve high levels of fault coverage as required for ASIL certifications without a significant effect on performance, power or area compared to the non-ASIL Ready NPX6 NPUs.
The NPX6FS NPUs are fully programmable and combine the flexibility of software solutions with the high performance and low power consumption of dedicated hardware.
The NPX6FS NPUs are supported by the ASIL D Ready ARC MetaWare MX Development Toolkit for Safety to help simplify the development of ISO 26262-compliant software.
The NPX6FS NPUs include state-of-the-art hardware safety features including diagnostic error injection, windowed watchdog timers, error classification, and software diagnostic tests as well as safety monitors and lockstep capabilities for safety-critical modules. The processors include dedicated safety mechanisms for ISO 26262 compliance and address the mixed criticality and virtualization requirements of next-generation zonal architectures.
Comprehensive safety documentation, including safety manuals, FMEDA and DFMEA reports, accelerate SoC-level functional safety assessments. These features enable designers to achieve high levels of fault coverage as required for ASIL certifications without a significant effect on performance, power or area compared to the non-ASIL Ready NPX6 NPUs.
The NPX6FS NPUs are fully programmable and combine the flexibility of software solutions with the high performance and low power consumption of dedicated hardware.
The NPX6FS NPUs are supported by the ASIL D Ready ARC MetaWare MX Development Toolkit for Safety to help simplify the development of ISO 26262-compliant software.
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Neural Processing Unit IP
- General Purpose Neural Processing Unit (NPU)
- ARC NPX Neural Processing Unit (NPU) IP supports the latest, most complex neural network models and addresses demands for real-time compute with ultra-low power consumption for AI applications
- Enhanced Neural Processing Unit for safety providing 32,768 MACs/cycle of performance for AI applications
- DPU for Convolutional Neural Network
- NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
- Highly scalable inference NPU IP for next-gen AI applications