5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+
You are here:
Energy-efficient 32-bit superscalar processor
C807 utilizes an 8-stage pipeline and dual-issue superscalar architecture, with a standard memory management unit, and can run Linux and other operating systems.
查看 Energy-efficient 32-bit superscalar processor 详细介绍：
- 查看 Energy-efficient 32-bit superscalar processor 完整数据手册
- 联系 Energy-efficient 32-bit superscalar processor 供应商
Block Diagram of the Energy-efficient 32-bit superscalar processor
CPU IP
- High Bandwidth Out-of-Order RISC-V CPU IP Core
- All in one solution for AI in RISC-V
- 2D (vector graphics) GPU IP Further advanced architecture for minimized CPU load and increased pixel performance in vector processing
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load
- High Bandwidth In-Order RISC-V CPU IP Core
- RISC-V Processor - RV12 - 32/64 bit, Single Core CPU