MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
eMMC/SDIO/SD
The IP is fully compliant with the following standards: JESD84-B51 eMMC5.1 specifications, SD3.01 specifications, and SDIO3.00 specifications.
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