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eMMC 5.1 Host Controller
The eMMC 5.0 Host Controller IP is a highly integrated host controller IP solution. This Host Controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. eMMC5.0 host interface is based on a standard 32-bit AXI bus which is used to transfer data and configure the IP.
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Block Diagram of the eMMC 5.1 Host Controller
emmc 5.1 host IP
- SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
- SD 5.1 / eMMC 5.1 Host Controller IP
- eMMC 5.1 /SD-SDIO3.0 Host Controller & PHY
- eMMC 5.1 Device Controller
- eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
- Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC