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eDP 1.5a RX PHY Samsung 14nm
The Qualitas eDP RX PHY IP supports the eDP RX v1.5a standard.
This core IP commonly used for connecting a timing controller (TCON) to a host processor.
This core IP commonly used for connecting a timing controller (TCON) to a host processor.
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Block Diagram of the eDP 1.5a RX PHY Samsung 14nm
Display IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VDC-M (VESA Display Compression-M) Encoder
- VDC-M (VESA Display Compression-M) Decoder
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs