MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
eDP 1.4 Receiver
特色
- Compliant with Embedded DisplayPort 1.4 specification
- Support for up to 4 Dual-Speed lanes at 1.62 Gbit/s and 2.7 Gbit/s
- Supports Enhanced Framing Mode
- Integrated High-bandwidth Digital Content Protection (HDCP) version 1.4
- Integrated Audio Clock Regeneration
- Deep-Color mode support up to 48-bit RGB/YCbCr Digital Video Output with selectable edge clocking
- Power-down modes
- 2.5 V I/O
- Panasonic 65 nm process
- Supports Advanced Link Power Management
- Supports GTC function
- Supports Panel Self Refresh function
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Block Diagram of the eDP 1.4 Receiver
eDP 1.4 Receiver IP
- DisplayPort Receiver Link Controller
- DP1.4 Receiver Controller
- Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
- Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
- eDisplayPort v1.4 Receiver Controller IP Core
- Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 28HPC