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DVB-T/DVB-H modulator
The proliferation of low-cost DVB-T/DVB-H demodulation and set-top-box products has opened up a wealth of opportunities for applications requiring low-cost broadband wireless audio/video/data links. Commodity products have largely been aimed at the broadcast market where the high volumes are at the demodulation end of the link. The Commsonic DVB-T Modulator allows exploitation of this technology by allowing the development of the modulator in low-cost FPGA or ASIC implementation. Applications include CCTV, wireless home networking, test equipment, etc.
This core is intended to provide a very efficient FPGA or ASIC implementation of all functions required to take the output from an MPEG-2 transport multiplexer and modulate it according to ETSI EN300 744 v1.5.1. The specification is fully supported for 2K, 4K and 8K COFDM modes as well as hierarchical transport streams. The standard output is a baseband I/Q digital pair for direct connection to a DAC. Alternative output configurations include a low IF or direct connection to standard Analog Devices Direct Digital Synthesizers (e.g. AD9857).
Every effort has been made to keep the size of the block to an absolute minimum in order to target the low-cost FPGA families, however this has not been at the expense of functionality. Synthesis directives are used wherever possible to remove a block within the design has functionality that may not be required for all applications.
This core is intended to provide a very efficient FPGA or ASIC implementation of all functions required to take the output from an MPEG-2 transport multiplexer and modulate it according to ETSI EN300 744 v1.5.1. The specification is fully supported for 2K, 4K and 8K COFDM modes as well as hierarchical transport streams. The standard output is a baseband I/Q digital pair for direct connection to a DAC. Alternative output configurations include a low IF or direct connection to standard Analog Devices Direct Digital Synthesizers (e.g. AD9857).
Every effort has been made to keep the size of the block to an absolute minimum in order to target the low-cost FPGA families, however this has not been at the expense of functionality. Synthesis directives are used wherever possible to remove a block within the design has functionality that may not be required for all applications.
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