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DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)
The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single output interface. The data coming from the 8 demodulators are multiplexed and decoded by the same engine. After decoding, 8 packet delineators do the demultiplexing and DVB-S2 de-framing before sending data to the output transport stream manager.
For a 258-MHz clock we may have a maximum data rate of 258 Mchannel-bit/s (megaLLRs)at the input to the FEC decoder. Advanced power-saving features have been implemented, the LDPC stops once the solution is sufficiently converged and the various blocks of the IC (tuner, demodulator, LDPC, Legacy FEC, and so on) may be completely shut down if not required. The device also supports Wake-on-network PID.
For a 258-MHz clock we may have a maximum data rate of 258 Mchannel-bit/s (megaLLRs)at the input to the FEC decoder. Advanced power-saving features have been implemented, the LDPC stops once the solution is sufficiently converged and the various blocks of the IC (tuner, demodulator, LDPC, Legacy FEC, and so on) may be completely shut down if not required. The device also supports Wake-on-network PID.
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